1. Technical Field
The present invention relates to a data transfer control device capable of transferring data in block units, and an information processing system that incorporates such a data transfer control device.
2. Background Art
A direct memory access (DMA) method is often used as means of transferring data at high speeds. With this DMA method, the generation of timing signals necessary for data transfer performed by a hardware device called a DMA controller. During data transfer, the transfer is controlled by the DMA controller, obviating the need for control by a program from an external controller (such as a CPU), and, at the end of transfer, tbe relevant status is posted to the external controller. Prior art examples of such a DNA controller are disclosed in Japanese Patent Application Nos. 55-97630 and 56-60933.
When the external controller sends a data transfer command to a DMA controller of this type, it specifies management information (hereinafter, this management information is called table data) that comprises a transfer start address and a transfer count for each of the transfer source and transfer destination. The area specified in this manner is transferred in sequence as one group of data blocks Note that a transfer end address could be used in this case instead of the transfer count, and also that the start address can be unnecessary if the transfer source or the transfer destination is simply an input port or output port.
With a DMA controller for disk memory such as a hard disk or magneto-optical disk, a read-ahead method and the Least Recently Used (LRU) method are often used. With this read-ahead method. when a command arrives from the controller to read an nth sector on the disk, the (n+1st)th and (n+2nd)th sectors are read ahead and the read-ahead data is stored in a buffer memory. With a DNA controller for a disk memory, reading data from the disk memory takes the most time. That is why if a plurality of sectors of data could be read with a single disk read command, the overall data transfer speed can be increased. The LRU method rearranges the excessive data that has been read out by this read-ahead method, and deletes data that is not accessed far a while from the data stored in the buffer memory. Thus, if excessive data is read by the read-ahead method and older data is deleted sequentially by the LRU method, as shown in FIG. 24, the data blocks are not arranged in sequence physically.
However, with a DMA controller using this conventional method, one group of data blocks can be specified far each transfer start command. This means that, to sequentially transfer groups of data blocks 400, 402, and 404 that are not arranged in sequence physically, as shown in FIG. 24, it is necessary to wait for the transfer of one group of data blocks to end before specifying the next data block, and then restart the data transfer. This creates a problem in that the program overhead for transfer control executed by the external controller is extremely large.
An LSI (hereinafter abbreviated to DMC-1) that solves the above-described problem with this type of DMA controller used as a disk memory controller has been developed. With this DMC-1, groups of data blocks can be specified for a single transfer start command, a management area for specifying data blocks is reserved in the buffer memory managed by the DMC-1, and start addresses 503 to 506 of each data block can be stored, as shown in FIG. 25A. This makes it possible to modify the transfer of data blocks that are not arranged physically in sequence, a transfer arranged logically in sequence. Table data for block specification within the DMC-1 also includes a host enable bit (H bit) 501 and a disk enable bit (D bit) 502. Thus if, for example, H=1 and D=0 (where 1 indicates true and 0 indicates false), those data blocks are transferred between the host (this is assumed to be mainly a SCSI interface) and the buffer memory. If H=0 and D=1, those data blocks are transferred between the disk and the buffer memory. This enables data transfer on both the host and disk sides with a single group of table data, facilitating the implementation of the read-ahead methods such as a cache method that is often used with disk memory.
However, with the DMC-1, the data block specification for one group can be done only per sector, which leads to a problem in that the size of the management area becomes extremely large. In other words, if, for example, 100 sectors are to be transferred, the table data shown in FIG. 25A is required for all of the 100 sectors, and thus an area capable of storing 100 sets of table data must be provided in the buffer memory. Another practical problem is raised when the upper limit of the area size is exceeded. In such case, the transfer must be carried out several times, making the control very difficult. Further, once the external controller issues a transfer start command, it is not possible to make the next data block specification until the transfer ends, raising the problem that the program overhead of the external controller becomes large if there is a large number of data blocks.
Subsequently, an LSI (hereinafter abbreviated to DMC-2) that improved upon the above-described problems with the DMC-1 was developed. With this DMC-2, concerning a disk-side transfer it is possible to specify a number of transfer sectors 508 in addition to the start addresses 510 to 512, as shown in FIG. 25C. Therefore, the DMC-2 differs from the above-described DMC-1 in that it is not necessary to specify the start addresses for all the sectors to be transferred, and physically continuous sectors can be summarized and specified as one data block. This point means that the program overhead of the external controller in the DMC-2 can be reduced in contrast with that of the DMC-1. In addition, the management area for specifying data blocks is reserved within the LSI with the DMC-2, unlike with the DMC-1, and this management area operates as A queue buffer. Therefore, if a previously specified area should become empty during a transfer operation, the next data block specification can be added, leading to a further decrease In the program overhead of the external controller. Further, a queue buffer is introduced in the DMC-2, even for data block specification on the host side, so that a block specification can be added during transfer.
However, with the above-described DMC-2, the bock specification on the host side requires the start addresses 513 to 515 and a number of transfer byte 516 to 518, as shown in FIG. 25B. In other words, data is transferred between the host and the buffer memory in byte units, and between the buffer memory and the disk in sector units. Therefore, when data is to be transferred between the host and the disk, the problem arises in that a number of transfer sectors must be converted into a number of transfer bytes, or vice versa. Further, from practical considerations of system operation, it is far more common to use a transfer unit that is a groups of sectors, such as a cluster or segment, rather than individual sectors. Therefore, if these transfers are specified in sector units, the specification information becomes redundant, and thus increases the program overhead of the external controller.
In this case, the data block specification information could be made common in the same way as in the previously described DMC-1, enabling the specification of a plurality of data blocks. Nevertheless, making the information common raises further problems which will be discussed below. For example, considering the case where the disk-side and host-side table data is made common and data is to be transferred from the disk side to the host side via the buffer memory. In this case, table data for data transfer between the disk and the buffer memory is stored in the management area of the DMC-2, and this table data is also used for the data transfer between the buffer memory and the host. However, since disk memory read and write operations usually take time, the data transfer on the disk side is slower than that on the host side. Further, since the management area that stores the table data in the DMC-2 has, for example, a two-stage queue buffer configuration, when two sets of table data from transfer between the disk and the buffer memory are stored in this queue buffer, and it is not possible to add new data to the table data for transfer between the buffer memory and the host. This raises the problem that data transfer between the buffer memory and the best has to wait until data transfer between the disk and the buffer memory has ended.
One solution to this problem that has been considered is not to keep the table data in common, as it is with the DMC-2, but to physically divide it. This does solve the above-described problem, but raises a different problem in that even if this table data is kept in common, the external controller has to specify table data for both sides, which is time-consuming.
Another problem concerns how to end the transfer operation as described below. In the DMC-2 the transfer ends when the queue buffer becomes empty. Therefore, if, for example, it is considered that the transfer speed on the host side is faster than that on the disk side on reading data from disk, it is highly possible that the management area on the host side becomes empty quicker, and therefore the transfer operation ends on the host side as soon as the management area becomes empty. This means that another transfer start command must be issued to transfer the remaining data blocks on the host side, thus raising the problem of increasing the program overhead of the external controller.
A final problem concerns the connections of the external interfaces. An external interface is typically a SCSI interface, but conventionally the above-described DMC-1 or DMC-2 and SCSI controller LSI are combined into a single system. Recent progress in integration has led to marketing such product which is the combination of the above-described two types of LSI on a single chip. However, the basic internal structure of such product is equivalent to two chips that are simply connected together. Thus, since each of the SCSI controller side and the DMC-1 (or DMC-2) side has an independent transfer count counter, the transfer count has to be set in two places. This causes bugs during program development. Further, if the circuitry is modified in an attempt to increase the magnitude of the transfer count, the number of stages of both counters must be increased. This leads increases the circuitry size, and thus reduces reliability.